Systems and methods for managed operational marginalization

ABSTRACT

Systems, methods, devices, circuits for data processing, and more particularly to data processing including operational marginalization capability.

FIELD OF THE INVENTION

Embodiments are related to systems and methods for data processing, andmore particularly to systems and methods for managed degradation of adata processing system.

BACKGROUND

Various data transfer systems have been developed including storagesystems, cellular telephone systems, radio transmission systems. In eachof the systems data is transferred from a sender to a receiver via somemedium. For example, in a storage system, data is sent from a sender(i.e., a write function) to a receiver (i.e., a read function) via astorage medium. The data processing includes application of various dataprocessing algorithms to recover originally written data. Suchprocessing results in a very small number of errors that in some casesare due to corruption of the originally received data. Such a level oferrors make it difficult to make adjustments to either correct for thetype of errors or make it difficult to characterize the quality of adevice.

Hence, for at least the aforementioned reasons, there exists a need inthe art for advanced systems and methods for data processing.

SUMMARY

Embodiments are related to systems and methods for data processing, andmore particularly to systems and methods for managed degradation of adata processing system.

Various embodiments of the present invention provide data processingsystems that include a known data based noise injection circuit and aprocessing circuit. The known data based noise injection circuit isoperable to: calculate a noise component based upon a data input and acorresponding known pattern; add a noise value derived from the noisecomponent to a corresponding instance of the data input to yield a noiseinjected output; and select one of the data input and the noise injectedoutput as a processing input. The processing circuit is operable toapply a data processing algorithm to the processing input to yield adata output.

This summary provides only a general outline of some embodiments of theinvention. The phrases “in one embodiment,” “according to oneembodiment,” “in various embodiments”, “in one or more embodiments”, “inparticular embodiments” and the like generally mean the particularfeature, structure, or characteristic following the phrase is includedin at least one embodiment of the present invention, and may be includedin more than one embodiment of the present invention. Importantly, suchphases do not necessarily refer to the same embodiment. Many otherembodiments of the invention will become more fully apparent from thefollowing detailed description, the appended claims and the accompanyingdrawings.

BRIEF DESCRIPTION OF THE FIGURES

A further understanding of the various embodiments of the presentinvention may be realized by reference to the figures which aredescribed in remaining portions of the specification. In the figures,like reference numerals are used throughout several figures to refer tosimilar components. In some instances, a sub-label consisting of a lowercase letter is associated with a reference numeral to denote one ofmultiple similar components. When reference is made to a referencenumeral without specification to an existing sub-label, it is intendedto refer to all such multiple similar components.

FIG. 1 shows a storage system including known pattern based noiseinjection circuitry in accordance with various embodiments of thepresent invention;

FIG. 2 depicts a data transmission system including known pattern basednoise injection circuitry in accordance with one or more embodiments ofthe present invention;

FIG. 3 shows a data processing circuit including a known pattern basednoise injection circuit in accordance with some embodiments of thepresent invention; and

FIGS. 4 a-4 b are flow diagrams showing a method for data processingrelying on known pattern based noise injection in accordance with someembodiments of the present invention.

DETAILED DESCRIPTION OF SOME EMBODIMENTS

Embodiments are related to systems and methods for data processing, andmore particularly to systems and methods for managed degradation of adata processing system.

Various embodiments of the present invention provide data processingsystems. The data processing systems include a known pattern based noiseinjection circuitry. Such known pattern based noise injection circuitryis operable to: calculate a noise component based upon a combination ofan equalized output and a known pattern that corresponds to the dataexpected to be received as equalized output; scale the noise componentto yield a scaled noise output; and add the scaled noise output to theequalized output to yield a noise injected output. Where managedoperational degradation is desired, the noise injected output isselected as a processing data input, and a bit error rate is calculatedbased upon the results achieved when processing the scaled noise output.In contrast, when standard data processing is desired, the equalizedoutput is selected as a processing data input.

Various embodiments of the present invention provide data processingsystems that include a known data based noise injection circuit and aprocessing circuit. The known data based noise injection circuit isoperable to: calculate a noise component based upon a data input and acorresponding known pattern; add a noise value derived from the noisecomponent to a corresponding instance of the data input to yield a noiseinjected output; and select one of the data input and the noise injectedoutput as a processing input. The processing circuit is operable toapply a data processing algorithm to the processing input to yield adata output.

In some instances of the aforementioned embodiments, the data processingsystem further includes a storage circuit operable to store the knownpattern. In some such instances, the known pattern is comprised ofexpected values of the data input pre-stored to the storage circuit. Invarious instances of the aforementioned embodiments, the known databased noise injection circuit is further operable to multiply the noisecomponent by a scalar value to yield a scaled noise component, whereinthe noise value is the scaled noise component. In some cases, the scalaris programmable.

In one or more instances of the aforementioned embodiments, the systemsfurther include a data detector circuit and a bit error rate monitorcircuit. The detector circuit is operable to apply a data detectionalgorithm to the processing input to yield a detected output. The biterror rate monitor circuit is operable to generate a bit error ratebased at least in part on a combination of the known pattern and thedetected output. In some cases, the bit error rate monitor is operableto XOR corresponding instances of the known pattern and the detectedoutput to yield an error indicator. In particular cases, the bit errorrate monitor is further operable to calculate a ratio of the number oftimes the error indicator indicates an error to a total number of bitsprocessed.

Other embodiments of the present invention provide methods for dataprocessing. The methods include: receiving a data input at a noiseinjection circuit; calculating a difference between the data input and aknown pattern by the noise injection circuit to yield a noise component;adding a noise value derived from the noise component to a correspondinginstance of the data input to yield a noise injected output; selectingone of the noise injected output and the data input as a processinginput; and applying a data processing algorithm to the processing inputto yield a data output. In some instances of the aforementionedembodiments, the methods further include storing the known pattern to astorage area of the noise injection circuit. In some cases, the knownpattern is comprised of expected values of the data input pre-stored tothe storage area. In one or more instances of the aforementionedembodiments, the methods further include scaling the noise component toyield a scaled noise component. In such cases, the noise value is thescaled noise component.

Yet other embodiments of the present invention provide storage devices.Such storage devices include: storage medium operable to maintain aknown read pattern; a head assembly disposed in relation to the storagemedium and operable to provide a sensed signal corresponding to theknown read pattern on the storage; and a read channel circuit. The readchannel circuit includes: an analog front end circuit operable toprovide an analog signal corresponding to the sensed signal; an analogto digital converter circuit operable to sample the analog signal toyield a series of digital samples; an equalizer circuit operable toequalize the digital samples corresponding to the data set to yield asample set; and a known data based noise injection circuit. The knowndata based noise injection circuit is operable to: calculate noisecomponents based upon the sample set and corresponding instances of aknown pattern; add noise values derived from the noise components tocorresponding instances of the sample set yield a noise injected output;and select one of the data input and the noise injected output as aprocessing input; and a processing circuit operable to apply a dataprocessing algorithm to the processing input to yield a data output.

In some instances of the aforementioned embodiments, the read channelcircuit further includes a storage circuit operable to store the knownpattern. In one or more cases, the known pattern is comprised ofexpected values of the data input pre-stored to the storage circuit. Invarious instances of the aforementioned embodiments, the known databased noise injection circuit is further operable to: multiply the noisecomponents by a scalar value to yield scaled noise components. In suchinstances, the noise values are the scaled noise components.

Turning to FIG. 1, a storage system 100 including a read channel circuit110 having known pattern based noise injection circuitry is shown inaccordance with various embodiments of the present invention. Theutilized known pattern corresponds to an input expected to be receivedby read channel circuit 110, and may be stored to a memory area of theread channel circuit 110 and accessed when desired. Storage system 100may be, for example, a hard disk drive. Storage system 100 also includesa preamplifier 170, an interface controller 120, a hard disk controller166, a motor controller 168, a spindle motor 172, a disk platter 178,and a read/write head 176. Interface controller 120 controls addressingand timing of data to/from disk platter 178. The data on disk platter178 consists of groups of magnetic signals that may be detected byread/write head assembly 176 when the assembly is properly positionedover disk platter 178. In one embodiment, disk platter 178 includesmagnetic signals recorded in accordance with either a longitudinal or aperpendicular recording scheme.

In a typical read operation, read/write head assembly 176 is accuratelypositioned by motor controller 168 over a desired data track on diskplatter 178. Motor controller 168 both positions read/write headassembly 176 in relation to disk platter 178 and drives spindle motor172 by moving read/write head assembly to the proper data track on diskplatter 178 under the direction of hard disk controller 166. Spindlemotor 172 spins disk platter 178 at a determined spin rate (RPMs). Onceread/write head assembly 176 is positioned adjacent the proper datatrack, magnetic signals representing data on disk platter 178 are sensedby read/write head assembly 176 as disk platter 178 is rotated byspindle motor 172. The sensed magnetic signals are provided as acontinuous, minute analog signal representative of the magnetic data ondisk platter 178. This minute analog signal is transferred fromread/write head assembly 176 to read channel circuit 110 viapreamplifier 170. Preamplifier 170 is operable to amplify the minuteanalog signals accessed from disk platter 178. In turn, read channelcircuit 110 decodes and digitizes the received analog signal to recreatethe information originally written to disk platter 178. This data isprovided as read data 103 to a receiving circuit. A write operation issubstantially the opposite of the preceding read operation with writedata 101 being provided to read channel circuit 110. This data is thenencoded and written to disk platter 178.

As part of a device characterization process, read channel circuit 110monitors a received input stream for a synchronization mark. Once thesynchronization mark is found, data received from the disk is modifiedby injecting a noise component generated based at least in part on aknown data pattern and the data accessed from disk platter 178. Thenoise being added is designed to raise a minimal error rate generallyyielded by read channel circuit 110 to an error rate that canmeaningfully characterize storage system 100. In some cases, the readchannel circuit 110 may include circuitry similar to that discussed inrelation to FIG. 3 below; and/or may operate similar to the methodsdiscussed below in relation to FIGS. 4 a-4 b.

It should be noted that storage system 100 may be integrated into alarger storage system such as, for example, a RAID (redundant array ofinexpensive disks or redundant array of independent disks) based storagesystem. Such a RAID storage system increases stability and reliabilitythrough redundancy, combining multiple disks as a logical unit. Data maybe spread across a number of disks included in the RAID storage systemaccording to a variety of algorithms and accessed by an operating systemas if it were a single disk. For example, data may be mirrored tomultiple disks in the RAID storage system, or may be sliced anddistributed across multiple disks in a number of techniques. If a smallnumber of disks in the RAID storage system fail or become unavailable,error correction techniques may be used to recreate the missing databased on the remaining portions of the data from the other disks in theRAID storage system. The disks in the RAID storage system may be, butare not limited to, individual storage systems such as storage system100, and may be located in close proximity to each other or distributedmore widely for increased security. In a write operation, write data isprovided to a controller, which stores the write data across the disks,for example by mirroring or by striping the write data. In a readoperation, the controller retrieves the data from the disks. Thecontroller then yields the resulting read data as if the RAID storagesystem were a single disk.

A data decoder circuit used in relation to read channel circuit 110 maybe, but is not limited to, a low density parity check (LDPC) decodercircuit as are known in the art. Such low density parity checktechnology is applicable to transmission of information over virtuallyany channel or storage of information on virtually any media.Transmission applications include, but are not limited to, opticalfiber, radio frequency channels, wired or wireless local area networks,digital subscriber line technologies, wireless cellular, Ethernet overany medium such as copper or optical fiber, cable channels such as cabletelevision, and Earth-satellite communications. Storage applicationsinclude, but are not limited to, hard disk drives, compact disks,digital video disks, magnetic tapes and memory devices such as DRAM,NAND flash, NOR flash, other non-volatile memories and solid statedrives.

In addition, it should be noted that storage system 100 may be modifiedto include solid state memory that is used to store data in addition tothe storage offered by disk platter 178. This solid state memory may beused in parallel to disk platter 178 to provide additional storage. Insuch a case, the solid state memory receives and provides informationdirectly to read channel circuit 110. Alternatively, the solid statememory may be used as a cache where it offers faster access time thanthat offered by disk platted 178. In such a case, the solid state memorymay be disposed between interface controller 120 and read channelcircuit 110 where it operates as a pass through to disk platter 178 whenrequested data is not available in the solid state memory or when thesolid state memory does not have sufficient storage to hold a newlywritten data set. Based upon the disclosure provided herein, one ofordinary skill in the art will recognize a variety of storage systemsincluding both disk platter 178 and a solid state memory.

Turning to FIG. 2, a data transmission system 200 including a receiver220 having known pattern based noise injection circuitry is shown inaccordance with various embodiments of the present invention. Theutilized known pattern corresponds to an input expected to be receivedby receiver 220, and may be stored to a memory area of receiver 220 andaccessed when desired. Data transmission system 200 includes atransmitter 210 that is operable to transmit encoded information via atransfer medium 230 as is known in the art. The encoded data is receivedfrom transfer medium 230 by a receiver 220. Receiver 220 processes thereceived input to yield the originally transmitted data.

As part of a device characterization process, receiver 220 monitors areceived input stream for a synchronization mark. Once thesynchronization mark is found, data received from the receiver 220 ismodified by injecting a noise component generated based at least in parton a known data pattern and the received data. The noise being added isdesigned to raise a minimal error rate generally yielded by receiver 220to an error rate that can meaningfully characterize data transmissionsystem 200. In some cases, receiver 220 may include circuitry similar tothat discussed in relation to FIG. 3 below; and/or may operate similarto the methods discussed below in relation to FIGS. 4 a-4 b.

FIG. 3 shows a data processing circuit 300 including known pattern basednoise injection circuit 339 in accordance with some embodiments of thepresent invention. Data processing circuit 300 includes an analog frontend circuit 310 that receives an analog signal 308. Analog front endcircuit 310 processes analog signal 308 and provides a processed analogsignal 312 to an analog to digital converter circuit 315. Analog frontend circuit 310 may include, but is not limited to, an analog filter andan amplifier circuit as are known in the art. Based upon the disclosureprovided herein, one of ordinary skill in the art will recognize avariety of circuitry that may be included as part of analog front endcircuit 310. In some cases, analog input signal 308 is derived from aread/write head assembly (not shown) that is disposed in relation to astorage medium (not shown). In other cases, analog input signal 308 isderived from a receiver circuit (not shown) that is operable to receivea signal from a transmission medium (not shown). The transmission mediummay be wired or wireless. Based upon the disclosure provided herein, oneof ordinary skill in the art will recognize a variety of source fromwhich analog input signal 308 may be derived.

Analog to digital converter circuit 315 converts processed analog signal312 into a corresponding series of digital samples 317. Analog todigital converter circuit 315 may be any circuit known in the art thatis capable of producing digital samples corresponding to an analog inputsignal. Based upon the disclosure provided herein, one of ordinary skillin the art will recognize a variety of analog to digital convertercircuits that may be used in relation to different embodiments of thepresent invention. Digital samples 317 are provided to an equalizercircuit 320. Equalizer circuit 320 applies an equalization algorithm todigital samples 317 to yield an equalized output 322. In someembodiments of the present invention, equalizer circuit 320 is a digitalfinite impulse response filter circuit as are known in the art. It maybe possible that equalized output 322 may be received directly from astorage device in, for example, a solid state storage system. In suchcases, analog front end circuit 310, analog to digital converter circuit315 and equalizer circuit 320 may be eliminated where the data isreceived as a digital data input.

Equalized output 322 is provided to a sync mark detector circuit 371that is operable to identify a pre-defined synchronization patternwithin equalized output 371. In some embodiments of the presentinvention, sync mark detector circuit 371 is operable to identify a 2Tpreamble pattern (i.e., a pattern that repeats every two periods)followed by a specific synchronization pattern. When the synchronizationpattern is identified, a sync found signal 372 is asserted high. Thissync found signal is used to synchronize the processing of user datainclude within equalized output 322. Based upon the disclosure providedherein, one of ordinary skill in the art will recognize a variety ofsync mark detector circuits that may be used in relation to differentembodiments of the present invention.

In addition, equalized output 322 is provided to known pattern basednoise injection circuit 339. Known pattern based noise injection circuit339 includes a noise calculation and scaling circuit 341, a selectorcircuit 332, a test selector circuit 301, a loop detector circuit 394, aknow pattern buffer 336, and a selector circuit 384. When an operationaldegradation of data processing circuit 300 is desired, a test input 303is asserted high to test selector circuit 301. In turn, test selectorcircuit 301 asserts a test selection signal 302. In particular, testselection signal 302 is asserted to select test data whenever both syncfound 372 (indicating user data is available as part of equalized output322) and test input 303 is asserted to select operational degradation.

Test selection signal 302 is provided to selector circuit 332. Whenevertest selection signal 302 is asserted to select test data, selectorcircuit 332 provides a noise injected output 388 as a processing output389. Otherwise, when test selection signal 302 is not asserted to selecttest data, selector circuit 332 provides equalized output 322 asprocessing output 389.

Processing output 389 is provided to a loop detector circuit 394 thatapplies a loop detection algorithm to yield a loop detector output 382.Loop detector circuit 394 may be any circuit known in the art thatapplies some type of algorithm designed to return a representation ofthe data from which analog signal 308 was derived. In one particularembodiment of the present invention, loop detector circuit 394 isoperable to determine timing feedback and other operations designed toalign the sampling of analog to digital converter circuit 315 with thereceived data set, and/or to adjust a gain applied by analog front endcircuit 310. Based upon the disclosure provided herein, one of ordinaryskill in the art will recognize a variety of circuits capable ofproviding a representation of the data from which analog signal 308 wasderived that may be used in relation to different embodiments of thepresent invention.

Known pattern 380 and loop detector output 382 are provided to aselector circuit 384. Selector circuit 384 provides one of known pattern380 or loop detector output 382 as a feedback output 330 based upon theassertion level of test selection signal 302. Feedback output 330 isprovided as a feedback to noise calculation and scaling circuit 341.When a sync mark is found, known pattern 380 is provided as feedbackoutput 330. Known pattern 380 is programmed to be the same as equalizedoutput 322 when the sensing of and processing of input 308 operatesproperly. Any difference between known pattern 380 and equalized output322 is typically due to noise. Thus, noise calculation and scalingcircuit 341 subtracts feedback output 330 from equalized output 322 tocreate a noise value. This noise value is then multiplied by a scalarvalue 399 to yield a scaled noise value. In some cases, scalar value 399is user programmable, while in other cases scalar value 399 is fixed.This scaled noise value is then added to equalized output 322 to yieldnoise injected output 388. The addition of the scaled noise to equalizedoutput 322 is done in such a way that the added scaled noise outputcorresponds to the instance of equalized output 322 from which theunderlying noise component was derived. As such, noise injected output388 includes the scaled noise that corresponds to actual noise inequalized output. In some embodiments of the present invention, thescalar value 399 is user programmable. The following equation representsan example operation of noise calculation and scaling circuit 341:noise injected output 388=equalized output 322+scaled noise value,where scaled noise value=scalar value 399*(equalized output 322−feedbackoutput 330).Again, where test selection signal 302 is asserted to select test data,selector circuit 332 provides noise injected output 388 as processingoutput 389. Thus, processing output 389 includes injected noise duringoperational degradation of data processing circuit 300.

Prior to identification of a sync mark when test selection signal 302 isasserted to select loop detector output 382 as feedback output 330, loopdetector output 382 is processed by a phase lock loop and flawscancircuitry block 334. The phase lock loop circuitry may be any circuitknown in the art that is useful for aligning sampling clocks to a serialinput, and the flawscan circuitry may be any flaw scan circuitry knownin the art. Upon finding a sync mark, test selection signal 302 isasserted such that selector circuit 332 provides noise injected output388 in place of equalized output 322 as processing output 389. Thisresults in a change to the latency from analog to digital convertercircuit 315 to the output of loop detector circuit 394 due to noisecalculation and scaling circuit 341. This change in latency isdetrimental to the immediate operation of the phase lock loop includedin phase lock loop and flawscan circuitry block 334. To compensate forthis, at the time selector circuit 332 switches from equalized output322 to noise injected output 388, selector circuit 384 provides knownpattern 380 to phase lock loop and flawscan circuitry block 334 in placeof loop detector output 382.

Additionally, loop detector output 382 is provided to a delay circuit373 where it is delayed to yield a delayed output 378 that is alignedwith the corresponding value of known pattern 380. The delay enforced bydelay circuit 373 corresponds to the latency through loop detectorcircuit 394. A bit error rate monitor circuit 379 calculates a bit errorrate based upon known pattern 380 and delayed output 382. In particular,bit error rate monitor circuit 379 XORs corresponding bits from knownpattern 380 and delayed output 382 to yield error indicators. Where theXOR is a logic ‘1’ there is a mismatch between the two outputsindicating an error. Bit error rate monitor circuit 379 calculates boththe number of mismatches identified (i.e., when the result of the XOR isa logic ‘1’) and the total number of bits processed. Bit error ratemonitor circuit 379 then generates a ratio of the number of mismatchesidentified to the total number of bits processed which is provided as abit error rate. As shown, known pattern 380 is used for two processes—tocalculate noise data by noise calculation and scaling circuit 341, andto calculate the bit error rate by bit error rate monitor circuit 379.In some embodiments of the present invention, known data 380 ismaintained in a memory in data processing circuit 300. The same memorymay be used to supply known data 380 to both noise calculation andscaling circuit 341 and to bit error rate monitor circuit 379. In othercases, known data 380 may be supplied from a memory apart from dataprocessing circuit 300 for use by one or both of bit error rate monitorcircuit 379 and/or noise calculation and scaling circuit 341.

In addition, processing output 389 is stored to a sample buffer circuit375 that includes sufficient memory to maintain one or more codewordsuntil processing of that codeword is completed through data detectorcircuit 325 and a data decoder circuit 350 including, where warranted,multiple “global iterations” defined as passes through both datadetector circuit 325 and data decoder circuit 350 and/or “localiterations” defined as passes through data decoding circuit 350 during agiven global iteration. Sample buffer circuit 375 stores the receiveddata as buffered data 377.

Data detector circuit 325 is a data detector circuit capable ofproducing a detected output 327 by applying a data detection algorithmto a data input. As some examples, the data detection algorithm may bebut is not limited to, a Viterbi algorithm detection algorithm or amaximum a posteriori detection algorithm as are known in the art. Basedupon the disclosure provided herein, one of ordinary skill in the artwill recognize a variety of data detection algorithms that may be usedin relation to different embodiments of the present invention. Datadetector circuit 325 may provide both hard decisions and soft decisions.The terms “hard decisions” and “soft decisions” are used in theirbroadest sense. In particular, “hard decisions” are outputs indicatingan expected original input value (e.g., a binary ‘1’ or ‘0’, or anon-binary digital value), and the “soft decisions” indicate alikelihood that corresponding hard decisions are correct. Based upon thedisclosure provided herein, one of ordinary skill in the art willrecognize a variety of hard decisions and soft decisions that may beused in relation to different embodiments of the present invention.

Detected output 327 is provided to a central queue memory circuit 360that operates to buffer data passed between data detector circuit 325and data decoder circuit 350. When data decoder circuit 350 isavailable, data decoder circuit 350 receives detected output 327 fromcentral queue memory 360 as a decoder input 356. Data decoder circuit350 applies a data decoding algorithm to decoder input 356 in an attemptto recover originally written data. The result of the data decodingalgorithm is provided as a decoded output 354. Similar to detectedoutput 327, decoded output 354 may include both hard decisions and softdecisions. For example, data decoder circuit 350 may be any data decodercircuit known in the art that is capable of applying a decodingalgorithm to a received input. Data decoder circuit 350 may be, but isnot limited to, a low density parity check decoder circuit or a ReedSolomon decoder circuit as are known in the art. Based upon thedisclosure provided herein, one of ordinary skill in the art willrecognize a variety of data decoder circuits that may be used inrelation to different embodiments of the present invention. Where theoriginal data is recovered (i.e., the data decoding algorithm converges)or a timeout condition occurs, data decoder circuit 350 provides theresult of the data decoding algorithm as a data output 374. Data output374 is provided to a hard decision output circuit 396 where the data isreordered before providing a series of ordered data sets as a dataoutput 398.

One or more iterations through the combination of data detector circuit325 and data decoder circuit 350 may be made in an effort to converge onthe originally written data set. As mentioned above, processing throughboth the data detector circuit and the data decoder circuit is referredto as a “global iteration”. For the first global iteration, datadetector circuit 325 applies the data detection algorithm withoutguidance from a decoded output. For subsequent global iterations, datadetector circuit 325 applies the data detection algorithm to buffereddata 377 as guided by decoded output 354. Decoded output 354 is receivedfrom central queue memory 360 as a detector input 329.

During each global iteration it is possible for data decoder circuit 350to make one or more local iterations including application of the datadecoding algorithm to decoder input 356. For the first local iteration,data decoder circuit 350 applies the data decoder algorithm withoutguidance from a decoded output 352. For subsequent local iterations,data decoder circuit 350 applies the data decoding algorithm to decoderinput 356 as guided by a previous decoded output 352. In someembodiments of the present invention, a default of ten local iterationsis allowed for each global iteration.

Turning to FIGS. 4 a-4 b are flow diagrams 400, 499 showing a method fordata processing relying on known pattern based noise injection inaccordance with some embodiments of the present invention. Followingflow diagram 400 of FIG. 4 a, an analog input is received (block 405).The analog input may be derived from, for example, a storage medium or adata transmission channel. Based upon the disclosure provided herein,one of ordinary skill in the art will recognize a variety of sources ofthe analog input. The analog input is converted to a series of digitalsamples (block 410). This conversion may be done using an analog todigital converter circuit or system as are known in the art. Of note,any circuit known in the art that is capable of converting an analogsignal into a series of digital values representing the received analogsignal may be used. The resulting digital samples are equalized to yieldan equalized output (block 415). In some embodiments of the presentinvention, the equalization is done using a digital finite impulseresponse circuit as are known in the art. Based upon the disclosureprovided herein, one of ordinary skill in the art will recognize avariety of equalizer circuits that may be used in place of such adigital finite impulse response circuit to perform equalization inaccordance with different embodiments of the present invention.

Sync mark detection is applied to the equalized output to identify async mark pattern therein (block 416). In some embodiments of thepresent invention, the sync mark detection is operable to identify a 2Tpreamble pattern (i.e., a pattern that repeats every two periods)followed by a specific synchronization pattern. When the synchronizationpattern is identified, a sync found signal is asserted. The pattern iscontinuously queried to identify a sync mark that may be used to alignuser data included within the received equalized output (block 417).Based upon the disclosure provided herein, one of ordinary skill in theart will recognize a variety of sync mark detector circuits and/ordetection methods that may be used in relation to different embodimentsof the present invention.

Where a sync mark is found (block 417), it is determined whether a testcontrol signal is asserted (block 418). The test control signal is auser programmable signal that is used to indicate whether operationaldegradation is selected or whether normal operation is selected. Wherethe test control signal is not asserted (i.e., normal operation isselected) (block 418), a loop detection algorithm is applied to theequalized output to yield a first loop output (block 450). The loopdetection algorithm may be applied by any circuit known in the art thatapplies some type of algorithm designed to return a representation ofthe data from which the analog input was derived. In one particularembodiment of the present invention, the loop detection algorithm isoperable to determine timing feedback and other operations designed toalign the sampling related to the analog to digital conversion, and/orto adjust a gain applied by an analog front end circuit. Based upon thedisclosure provided herein, one of ordinary skill in the art willrecognize a variety of loop detection algorithms capable of providing arepresentation of the data from which the analog input was derived thatmay be used in relation to different embodiments of the presentinvention. Flawscan and phase lock loop processing is performed on thefirst loop output in accordance with processes known in the art (block455). In addition, the equalized output is buffered as a detector input(block 420).

Alternatively, where the test control signal is asserted (i.e., degradedoperation is selected) (block 418), a known patter is subtracted fromthe equalized output to yield a noise component (block 460). The knownpattern is programmed to be the same as the equalized output when thesensing of and processing of the received analog input operatesproperly. Thus, for example, where the method is used in relation to ahard disk drive, the known pattern is programmed to be an expectedequalized output achieved when reading a defined location on the storagemedium where a defined pattern is stored. Any difference between theknown pattern and the equalized output is typically due to noise. Thenoise component is then multiplied by a scalar value to yield a scalednoise output (block 465). In some cases, the scalar value is userprogrammable, while in other cases the scalar value is fixed. The scalednoise output is then added to the equalized output such that the addedscaled noise output corresponds to the instance of the equalized outputfrom which the underlying noise component was derived (block 470).

The loop detection algorithm is applied to the noise injected output toyield a second loop output (block 480). Again, the loop detectionalgorithm may be applied by any circuit known in the art that appliessome type of algorithm designed to return a representation of the datafrom which the analog input was derived. In one particular embodiment ofthe present invention, the loop detection algorithm is operable todetermine timing feedback and other operations designed to align thesampling related to the analog to digital conversion, and/or to adjust again applied by an analog front end circuit. Based upon the disclosureprovided herein, one of ordinary skill in the art will recognize avariety of loop detection algorithms capable of providing arepresentation of the data from which the analog input was derived thatmay be used in relation to different embodiments of the presentinvention.

The second loop output is aligned in time with corresponding instancesof the known pattern, and the corresponding instances of the knownpattern and the second loop output are individually XORd to yield a biterror output (block 485). Where the XOR results in a logic ‘1’ there isa mismatch between the two outputs indicating an error. The number ofmismatches identified (i.e., when the result of the XOR is a logic ‘1’)is calculated, and the total number of bits processed is calculated. Abit error rate is calculated as a ratio of the number of mismatchesidentified to the total number of bits processed which is provided as abit error rate (block 490).

In addition, where the test control signal is asserted (i.e., degradedoperation is selected) (block 418), the noise injected output isbuffered as a detector input (block 495). It is determined whether adata detector circuit is available to process the buffered detectorinput (i.e., either the equalized output in a normal processing mode, orthe noise injected output in a degraded operation mode (block 425).Where a data detector circuit is available to process a data set (block425), the next available equalized output from the buffer is selectedfor processing (block 430). A data detection algorithm is then appliedto the selected equalized output to yield a detected output (block 437).The data detection algorithm may be, for example, a Viterbi algorithmdata detection or a maximum a posteriori data detection algorithm. Thedetected output (or a derivative thereof) is then stored to a centralmemory (block 445).

Turning to FIG. 4 b and following flow diagram 499, it is determinedwhether a data decoder circuit is available (block 401) in parallel tothe previously described data detection process of FIG. 4 a. The datadecoder circuit may be, for example, a low density parity check datadecoder circuit as are known in the art. Where the data decoder circuitis available (block 401) the next derivative of a detected output isselected from the central memory (block 406). The derivative of thedetected output may be, for example, an interleaved (shuffled) versionof a detected output from the data detector circuit. A first localiteration of a data decoding algorithm is applied by the data decodercircuit to the selected detected output to yield a decoded output (block411). It is then determined whether the decoded output converged (e.g.,resulted in the originally written data as indicated by the lack ofremaining unsatisfied checks) (block 416).

Where the decoded output converged (block 416), it is provided as adecoded output codeword to a hard decision output buffer (e.g., are-ordering buffer) (block 421). It is determined whether the receivedoutput codeword is either sequential to a previously reported outputcodeword in which case reporting the currently received output codewordimmediately would be in order, or that the currently received outputcodeword completes an ordered set of a number of codewords in which casereporting the completed, ordered set of codewords would be in order(block 456). Where the currently received output codeword is eithersequential to a previously reported codeword or completes an ordered setof codewords (block 456), the currently received output codeword and,where applicable, other codewords forming an in order sequence ofcodewords are provided to a recipient as an output (block 461).

Alternatively, where the decoded output failed to converge (e.g., errorsremain) (block 416), it is determined whether the number of localiterations already applied equals the maximum number of local iterations(block 426). In some cases, a default seven local iterations are allowedper each global iteration. Based upon the disclosure provided herein,one of ordinary skill in the art will recognize another default numberof local iterations that may be used in relation to differentembodiments of the present invention. Where another local iteration isallowed (block 426), the data decoding algorithm is applied to theselected data set using the decoded output as a guide to update thedecoded output (block 431). The processes of blocks starting at block416 are repeated for the next local iteration.

Alternatively, where all of the local iterations have occurred (block426), it is determined whether all of the global iterations have beenapplied to the currently processing data set (block 436). Where thenumber of global iterations has not completed (block 436), the decodedoutput is stored to the central queue memory circuit to await the nextglobal iteration (block 441). Alternatively, where the number of globaliterations has completed (block 436), an error is indicated and the dataset is identified as non-converging (block 446).

It should be noted that the various blocks discussed in the aboveapplication may be implemented in integrated circuits along with otherfunctionality. Such integrated circuits may include all of the functionsof a given block, system or circuit, or a subset of the block, system orcircuit. Further, elements of the blocks, systems or circuits may beimplemented across multiple integrated circuits. Such integratedcircuits may be any type of integrated circuit known in the artincluding, but are not limited to, a monolithic integrated circuit, aflip chip integrated circuit, a multichip module integrated circuit,and/or a mixed signal integrated circuit. It should also be noted thatvarious functions of the blocks, systems or circuits discussed hereinmay be implemented in either software or firmware. In some such cases,the entire system, block or circuit may be implemented using itssoftware or firmware equivalent. In other cases, the one part of a givensystem, block or circuit may be implemented in software or firmware,while other parts are implemented in hardware.

In conclusion, the invention provides novel systems, devices, methodsand arrangements for out of order data processing. While detaileddescriptions of one or more embodiments of the invention have been givenabove, various alternatives, modifications, and equivalents will beapparent to those skilled in the art without varying from the spirit ofthe invention. Therefore, the above description should not be taken aslimiting the scope of the invention, which is defined by the appendedclaims.

What is claimed is:
 1. A data processing system, the data processing system comprising: a known data based noise injection circuit operable to: calculate a noise component based upon a data input and a corresponding known pattern; add a noise value derived from the noise component to a corresponding instance of the data input to yield a noise injected output; and select one of the data input and the noise injected output as a processing input; a detector circuit operable to apply a data detection algorithm to the processing input to yield a detected output; and a bit error rate monitor circuit operable to generate a bit error rate based at least in part on a combination of the known pattern and the detected output.
 2. The data processing system of claim 1, wherein the data processing system further comprises: a storage circuit operable to store the known pattern.
 3. The data processing system of claim 2, wherein the known pattern is comprised of expected values of the data input pre-stored to the storage circuit.
 4. The data processing system of claim 1, wherein the known data based noise injection circuit is further operable to: multiply the noise component by a scalar value to yield a scaled noise component, wherein the noise value is the scaled noise component.
 5. The data processing system of claim 4, wherein the scalar is programmable.
 6. The data processing system of claim 1, wherein the bit error rate monitor is operable to XOR corresponding instances of the known pattern and the detected output to yield an error indicator.
 7. The data processing system of claim 6, wherein the bit error rate monitor is further operable to calculate a ratio of the number of times the error indicator indicates an error to a total number of bits processed.
 8. The data processing system of claim 1, wherein the processing circuit comprises: a data decoder circuit operable to apply a data decoding algorithm to a decoder input derived from the detected output to yield the data output.
 9. The data processing system of claim 8, wherein the data decoder circuit is a low density parity check decoder circuit.
 10. The data processing system of claim 1, wherein the data detector circuit is selected from a group consisting of: a maximum a posteriori data detector circuit, and a Viterbi algorithm data detector circuit.
 11. The data processing system of claim 1, wherein the system is implemented as an integrated circuit.
 12. A method for data processing, the method comprising: receiving a data input at a noise injection circuit; calculating a difference between the data input and a known pattern by the noise injection circuit to yield a noise component; adding a noise value derived from the noise component to a corresponding instance of the data input to yield a noise injected output; selecting one of the noise injected output and the data input as a processing input; and applying a data detection algorithm to the processing input to yield a detected output; and using a bit error rate monitor circuit to generate a bit error rate based at least in part on a combination of the known pattern and the detected output.
 13. The method of claim 12, wherein the method further comprises: storing the known pattern to a storage area of the noise injection circuit.
 14. The method of claim 13, wherein the known pattern is comprised of expected values of the data input pre-stored to the storage area.
 15. The method of claim 12, the method further comprising: scaling the noise component to yield a scaled noise component, wherein the noise value is the scaled noise component.
 16. A storage device, the storage device comprising: a storage medium operable to maintain a known read pattern; a head assembly disposed in relation to the storage medium and operable to provide a sensed signal corresponding to the known read pattern on the storage medium; a read channel circuit including: an analog front end circuit operable to provide an analog signal corresponding to the sensed signal; an analog to digital converter circuit operable to sample the analog signal to yield a series of digital samples; an equalizer circuit operable to equalize the digital samples corresponding to the data set to yield a sample set; a known data based noise injection circuit operable to: calculate noise components based upon the sample set and corresponding instances of a known pattern; add noise values derived from the noise components to corresponding instances of the sample set yield a noise injected output; and select one of the data input and the noise injected output as a processing input; a detector circuit operable to apply a data detection algorithm to the processing input to yield a detected output; and a bit error rate monitor circuit operable to generate a bit error rate based at least in part on a combination of the known pattern and the detected output.
 17. The storage device of claim 16, wherein the read channel circuit further comprises: a storage circuit operable to store the known pattern.
 18. The storage device of claim 17, wherein the known pattern is comprised of expected values of the data input pre-stored to the storage circuit.
 19. The storage device of claim 16, wherein the known data based noise injection circuit is further operable to: multiply the noise components by a scalar value to yield scaled noise components, wherein the noise values are the scaled noise components.
 20. The storage device of claim 19, wherein the scalar is programmable. 